1. Field of the Invention
The present invention relates to method of manufacturing complimentary field effect transistor devices (CMOS), and more particularly to form field isolation for CMOS that requires fewer process steps.
2. Description of the Invention
The conventional method of manufacturing a semiconductor substrate having P and N wells, and field oxide isolation regions electrically isolating the wells, is described and claimed in U.S. Pat. No. RE31,079. In this method, the P and N wells are formed in a semiconductor substrate. A pad oxide layer and an overlying layer of silicon nitride are deposited on the substrate and a first resist mask is deposited, exposed and developed to define the field oxide regions. These regions are opened up in the underlying oxide and nitride layers. A second resist layer is deposited, exposed and developed to cover one of the wells. Ions are implanted in the defined field oxide regions in the exposed well region using the oxide and nitride layers as a mask. After the second resist layer is removed, a thin resist layer is deposited, exposed and developed to cover the opposite well area, and opposite type ions implanted through the defined field oxide region openings in the oxide and nitride layers. Subsequently the third resist layer is removed and the substrate is exposed to an oxidizing environment to form field oxide regions in the openings in the nitride layer. The oxide layer and nitride layers are removed and the substrate further processed to form a complimentary metal over silicon devices, Note that the process requires three separate masking steps.
U.S. Pat. No. 5,141,882 to Komori et al, describes a process for forming a similar device structure. This process requires many masking operations. U.S. Pat. No. 5,086,012 to Sik also describes techniques for fabricating field oxide regions on substrates provided with N and P type wells. However, the patent also requires three or more steps and uses a thick deposited oxide rather than a thermally grown field oxide.
In semiconductor fabrication, each operation adds to the final cost of the device produced, and also presents the potential for reducing the yield. Thus, it is desirable to reduce the number of process operations in order to reduce cost and increase the yield. All of the prior art fabrication techniques use a least three or more masking operations to form field oxide isolation regions complete with channel inversion layers beneath the isolation regions in applications requiring N and P wells, as in complimentary type devices.